The exemplary embodiments of this invention relate generally to semiconductor devices and methods to fabricate them and, more specifically, exemplary embodiments of this invention relate to a class of devices known as metal high dielectric constant (high-k or MHK) transistors.
MHK transistors are experiencing extremely active development in the industry. One observed problem relates to the presence of an elevated outer fringe capacitance (Cot), on the order of 40-80 aF/μm. The elevated value of Cof is of concern, in that it at least impairs high frequency operation of the MHK transistor.
In U.S. Pat. No. 7,164,189 B2 Chien-Chao Huang et al. describe a method that includes providing a semiconductor substrate including a polysilicon or a metal gate structure including at least one overlying hardmask layer; forming spacers selected from the group consisting of oxide/nitride and oxide/nitride/oxide layers adjacent the polysilicon or metal gate structure; removing the at least one overlying hardmask layer to expose the polysilicon or metal gate structure; carrying out an ion implant process; carrying out at least one of a wet and dry etching process to reduce the width of the spacers; and, forming at least one dielectric layer over the polysilicon or metal gate structure and spacers in one of tensile and compressive stress.
In U.S. Pat. No. 6,448,613 B1 Bin Yu describes a field effect transistor that is fabricated to have a drain overlap and a source overlap to minimize series resistance between the gate and the drain and between the gate and the source of the field effect transistor. The parasitic Miller capacitance formed by the drain overlap and the source overlap is to be reduced by forming a depletion region at the sidewalls of the gate structure of the field effect transistor. The depletion region is formed by counter-doping the sidewalls of the gate structure. The sidewalls of the gate structure at the drain side and the source side of the field effect transistor are doped with a type of dopant that is opposite to the type of dopant within the gate structure. Such dopant at the sidewalls of the gate structure forms a respective depletion region from the sidewall into approximately the edge of the drain overlap and source overlap that extends under the gate structure to reduce the parasitic Miller capacitance formed by the drain overlap and the source overlap.
At least one drawback of this latter approach is that it does not address the reduction of parasitic Miller capacitance when metal-like materials (such as TiN) are used.